1. Field of the Invention
The present invention relates to a wafer-leveled chip packaging structure and method thereof, and more particularly, to a wafer-leveled chip packaging structure and method thereof for forming a wafer-leveled chip package by a wafer-leveled fabrication process.
2. Description of the Related Art
A semiconductor package chip is generally encapsulated into a plastic or ceramic material, which refers to level one packaging. As a rule, the package is required to support and protect the chip, increase the heat dissipation efficiency, and provide a system for distributing the electrical power and signals input and/or output the chip. Sometimes, the package is also used for testing the performance of the chip.
An important indication to verify the advancement of the chip packaging techniques is to the ratio of the package area to the chip area. The closer the ratio to 1, the better the technique is. Several well-known chip-packaging techniques are as follows. (1) Dual-in-line packages (DIP) are initially adopted for packaging memory chips. However, the size of the DIP is much larger than the chip and occupies a significant portion of the mounting areas. Thus, the DIP is insufficient. (2) Thin-small-outline packages (TSOP) provide leads around the package chip. The TSOP is suitable for mounting lines on the surface of a PCB by surface mount technique (SMT). Thus, TSOP is reliable, suitable for high frequency applications and easy to operate with. (3) Ball grid array (BGA) packages have been widely used in a large-scale integrated circuit package application such as the memory of the notebook computers. Although the power consumption increases as a result of the BGA package technique, the chips packaged therein have improved electrical and thermal performances, thus improving the reliability thereof. Also, though the number of I/O leads increases, the space between leads of the BGA package remains unchanged so as to be capable of increasing the product yield. Furthermore, the thickness and weight of the memory packaged are reduced. Besides, the signal transmission delays of the chips become less significant and thus the applicable frequency domain of the BGA package is broadened. (4) Chip scale packages (CSP) can reduce the ratio of the package area to the chip area to be less than 1.5. Comparing to the BGA package, the volume of a CSP memory product is smaller than that of a BGA package memory product. Besides, the CSP can have higher capacity but better heat dissipation than the BGA package. In addition, due to its significantly increased electrical performance, reliability and high system stability, the CSP has become the popular memory package technique for packaging a variety of products, such as DRAM.
Specifically speaking, the chip scale package (CSP) generally comprises a chip attaching to the surface of a substrate, wherein the substrate includes plural external contacts for electrically connecting the external device with the chip packaged therein. The substrate for the CSP comprises a flexible material such as a polymer tape, a rigid material such as silicon, ceramics or glass. The external contacts may include solder balls arranged in a dense manner such as the ball grid array (BGA) or a fine ball grid array (FBGA). Such high-density arrays can provide the chip scale package with a high input/output capability. For example, the FBGA of the CSP can have hundreds of solder balls in a unit area.
In addition, the form of central leads of memory chip packaged with the CSP can effectively shorten the signal transmitting paths. Thus, the CSP can lower the degree of the signal attenuation and increase the anti-interference and anti-noise performances of the chip packaged therein. As a result, the access time of the CSP is faster than the BGA by about 15% to 20%.
In the CSP, the memory chip is soldered to the PCB with plural solder balls which have large contact areas with the PCB, the heat generated by the memory chip during the operation can be easily transferred to the PCB for heat dissipation. On the other hand, the memory chip of the TSOP is soldered to the PCB with the leads of the chip. Therefore, the contact area between the solder and the PCB is much smaller and it is difficult to transfer heat from the chip to the PCB. Besides, the CSP can dissipate heat by its back face efficiently and be constructed compactly, whereby much unnecessary electric power consumption can be eliminated. Correspondingly, the chip packaged with the CSP can have low power consumption and lowered working temperature in comparison with the chips packaged with other package technology.
In the industry, especially in the wireless communication industry, the recent development of the chip scale packages is focused not only on reducing power consumption and packaging volume, but also on increasing the packaging density of the memory chip and performance. Therefore, stackability of the chip scale package is one of the solutions for increasing the packaging density of the memory chip and providing the chip package structure and method thereof with stackable chip scale packages are the objects of the present invention.